This invention is directed to a semiconductor device such as a Metal-Insulator-Semiconductor (MIS) type capacitor, and more particularly to a one transistor type dynamic random access memory.
Currently, efforts are being made to increase integration density or elements per chip of semiconductor integrated circuits. In semiconductor devices thus far manufactured when maximizing integration density, it is necessary to reduce the area occupied by each element. However, with regard to the capacitor element of the memory cell, there is a limitation on the reduction in the size of the area it occupies because, as its area is reduced, electric charges that can be accumulated therein are also reduced.
Particularly in the case of a one transistor type memory cell which contains therein a capacitor element, reduction of the area of the capacitor element brings about lessening of the accumulated electric charges, namely the reduction of the magnitude of read signals, as well as lowering of the tolerance against noises from outside.
Against this background, attempts are being made to utilize, as an insulating film of the capacitor element explained above, a film made of dielectric material which has a higher dielectric constant than that of silicon dioxide being currently used extensively. This a move will make it possible to reduce the area occupied by the capacitor element without lessening overall accumulated electric charges through an increase of the capacitance per unit area.
Insulating film which possesses a higher dielectric constant than the silicon dioxide film may be found, for example, among the films made of silicon nitride (Si.sub.3 N.sub.4), alumina (Al.sub.2 O.sub.3), tantalum oxide (Ta.sub.2 O.sub.5), titanium oxide (TiO.sub.2) and the like. These insulating films, however, form surface states due to crystal defects or dangling bonds and capture electric charges as has never been experienced with the conventional silicon dioxide film. Furthermore, in addition to the surface states, charge capturing centers or traps are formed within the insulating film, the traps capture electric charges due to tunnel current from the surface and so forth.
Because of the surface states and the capturing of electric charges at traps, an inversion layer is formed at the surface of a silicon substrate as time goes by, so that electric charges accumulated by the capacitor element vary as time passes. Furthermore, electric charges trapped at capturing centers are not all discharged at the time of reading, reflecting the decrease in electric charges actually accumulated.
In preventing the decrease of accumulated electric charges due to the trapping of charges at capturing centers, an effective method has been found wherein impurities creating a region of a conductivity type opposite to that of a silicon substrate are diffused near the surface of the silicon substrate and under the insulating film of the capacitor element described above to form in advance an inversion layer. Further, formation of a region of a conductivity type which is opposite to that of the substrate under the insulating film of said capacitor element will turn the MIS type capacitor itself in to a depletion mode. In the conventional enhancement mode MIS capacitor, charging is effective only up to a voltage which is equal to the voltage applied to an upper electrode of the capacitor which is normally connected to a power source minus the threshold voltage under which an inversion layer is formed near that part of the substrate surface having the MIS structure providing the capacitance. The result obtained by the method described above is that it is possible to charge with the capacitor voltage of the power source, and this increases the number of electric charges accumulated at the capacitor.
One of the most difficult problems experienced in applying the above method of forming a region of a conductivity type opposite to that of the substrate near the survace of the substrate is the alignment of the region of opposite conductivity type and the upper electrode of the capacitor. In other words, where the capacitor electrode is extended to a region beyond the region having a conductivity type opposite to that of the substrate, there is created a gap in the semiconductor substrate between the transfer gate portion and the capacitor element where the channel is cut off, and the gap forms a potential barrier to the carriers which charge the capacitor. Because of this, there is either a voltage loss at the time of writing by the data line or, according to the circumstances, the data line and the capacitor element are not connected via the transfer gate portion. Both of these exert an adverse effect on the operation of the random access memory. Conversely, where there is a capacitor electrode inside the region of opposite conductivity type which extends under a part of the transfer gate, the effective length of the transfer gate portion is accordingly shortened, and the so-called short channel effect is caused, and the threshold voltage is lowered or, according to the circumstances, the data line and the capacitor element are connected by leakage current due to a punch through phenomenon, which deteriorates the memory retention characteristics considerably. This is also disadvantageous.
And thus, in forming the region of opposite conductivity type described above, an extremely high precision technique is required for the alignment of the capacitor element. However, even when an exposure is made by electron beams, misalignment on the order of .+-.0.2 .mu.m cannot be avoided. Because of this, a substantial decrease in the manufacturing yield is presently being experienced.
Japanese Patent Publication (Unexamined) No. 59384 of 1978 published on May 29, 1978 discloses an invention titled: An N-channel MOS Silicon Gate RAM Cell. In that publication, there is disclosed an art of forming a region at the surface of a silicon substrate in such a manner that the region is to have a conductivity type which is opposite to that of the silicon substrate. Referring to FIG. 1 which shows in cross-section a part of a silicon substrate for fabricating the titled RAM cell, a p-type silicon substrate 1 is covered with a photoresist film 2 which has been patterned in a known manner. The photoresist film 2 is exposed to ultra violet light through a mask which shields a region covering where impurity ions are to be implanted. Ions of phosphorus are then driven into the region 3 where the RAM cell is to be fabricated at 150 KeV, with a dosage on order of 1.times.10.sup.12 /cm.sup.2. And thus, region 4 of n-type is formed near the surface of the p-type silicon substrate covered with a film 5 of silicon dioxide. The publication does not teach, however, how the alignment is effected, nor does it disclose any use of insulating film made of a material other than silicon dioxide.
Japanese Patent Publication (Unexamined) No. 76687 of 1978 published on July 7, 1978 is for a patent application in which the invention of said application is titled: A Semiconductor Memory Device.
Referring to FIGS. 2 and 3, ions of phosphorus, with a dosage in order of 5.times.10.sup.12 /cm.sup.2 are implanted into a p-type silicon substrate 11 or 11' near the surface of the substrate where a memory element is to be fabricated. As a result, an n-type region 14 or 14' is formed in the substrate 11 or 11' under a gate insulating film 12 or 12' of the memory capacitor on which is formed a capacitor electrode 13 or 13' of the memory capacitor. However, the publication does not teach how the alignment is done in this ion implantation, nor does it suggest any use of an insulating film other than a film made of silicon dioxide.